The present invention relates generally to a semiconductor package and a method for manufacturing the same, and more particularly to a semiconductor package having side walls formed around a semiconductor chip to increase the bonding area of the semiconductor chip package.
Semiconductor chips capable of storing large amounts of data and processing the data rapidly and semiconductor packages utilizing such semiconductor chips have been developed. Chip scale packages that are no more than about 100% to 105% of the size of semiconductor chips have been disclosed in the art.
One such chip scale package is a wafer level package, which includes a semiconductor chip, bonding pads formed on the semiconductor chip, re-distribution lines connected with the bonding pads, and solder balls placed on the re-distribution lines. In the wafer level package above, the size of the semiconductor package considerably decreases, because the solder balls are placed on the semiconductor chip. The solder balls are attached to the re-distribution lines and placed on the semiconductor chip according to the international standard of Joint Electron Device Engineering Council (JEDEC).
As semiconductor chip manufacturing processes continue to evolve, the size of the semiconductor chip gradually decreases. Therefore, problems associated with the decrease in the size of the semiconductor chip, in that it is difficult to attach solder balls on the semiconductor chip according to the international standard of JEDEC.